Layout of Capacitor
In principle, capacitor is nothing but two adjacent conductor plates with certain type of dielectric in-between. The capacitance is calculated based on the following formula:
If d and ε are constants and the area is a rectangle, this formula can be modified as:
Therefore, to layout a capacitor, we have to figure out the geometric parameters of the rectangle based on C and c, then draw it!
In the process (C5N_SUBME, λ=0.30μm) we are using, the two polysilicon (poly and elec, also known as poly2) are a proper pair to form a capacitor. The thin silicon dioxide between these adjacent layers yields good capacitance value per unit area. This type of capacitor is called poly-poly2 capacitor.
A sample of how to construct a 100fF (100E-15) poly-poly2 capacitor with a width of 9μm (30λ) is given to illustrate the layout process.
c(poly-poly2) = 0.800fF/μm2
→ s = C/c = 100f / 0.800f = 125
→ l = s/w = 125 / 9 = 13.89
→ round l to the nearest multiple of ½λ remember, we can only draw geometric of multiple ½λ!!
So if w is given as 10μm, you have to convert it to 10.05μm before you get started.
→ l = 13.95 = 46.5λ
ii) Draw poly and elec layers
Draw a 9μm x 13.95μm rectangle with elec (yellow). Then cover it with a poly (red) rectangle, which exceed every side of elec rectangle by 3μm. (You will see why we need the extra 3μm soon.)
iii) Cover the elec rectangle with M1_ELEC contacts and a metal1 rectangle
Use as many M1_ELEC contact as possible, without violating DRC, to cover the whole effective capacitance area (elec). Then cover the elec with a metal rectangle. The purpose of these contacts and metal1 is to minimize parasitic resistance.
iv) Cover the 3μm extended poly edge with M1_POLY contacts and metal1
Use as many M1_POLY contacts as possible, without violating DRC, to cover the extended poly edge. (Now you understand where this 3μm comes from. Each M1_POLY is 1.2μm wide and DRC requires 1.8μm between the contact and elec.) Then cover the M1_POLY contacts with metal1 as shown in figure 3. The purpose of these contacts is also to minimize parasitic resistance.
v) Draw a n-well to cover the whole capacitor
Draw a n-well to cover the poly rectangle with 0.6μm extension to fulfill DRC requirement. The purpose of this n-well is to minimize field leakage.
vi) Place Pins
Place a metal2 POS pin and a M2_M1 contact on top of a M1_POLY contact. Place a metal2 NEG pin and a M2_M1 contact on top of a M1_ELEC contact. Of course you can move the pins outside and use metal2 to connect them to the respective contacts.
vii) DRC check
Check DRC and correct all errors.
Do an Extraction without any switch and open the extracted view. A capacitor symbol should be placed at the upper-left corner of the inner rectangle. Choose the symbol and check its value to ensure your layout is correct. You are not going to get an exact match since the adjustment we made to fulfill the ½λ requirement but a reasonable error is allowed.
Thus we complete a 100fF capacitor layout.